FPGA Replay Audio Framework Example

This guide is a work in progress. Please Contact me with comments/issues that may arise whilst following along.

The starting point for this guide is a “getting-started” core, a minimal core which does little beyond configuring the FPGA to display a blank screen but makes an ideal starting point for experimenting with the Replay Framework.

After following this guide you should not only have a better understanding of a few entities within the Replay framework but also a core that streams an audio file off of an SD card and plays it back via the on-board DAC as demonstrated in the below youtube video (minus the audio visualiser).

NOTE: This is not an in-depth look at the framework, only a small part is covered in this guide and numerous details are glossed over. I however hope this will serve as a useful overview and introduction to the framework, providing a foundation to delve deeper into specific parts on your own.

Prerequisites

It is assumed you already have the Xilinx ISE development environment setup and are able to build the loader core, transfer it to an SD card and run it either as a replacement for the root loader core or placed within a sub-directory and loaded via “Load Target”.

If that makes no sense to you, a summary of the steps for Linux can be found in the first half of the Programming the Replay Board using VHDL blog post and further assistance found on the FPGA Arcade Forum

In addition, I assume you are familiar with the basic syntax for VHDL although I also assume you’re a complete novice (as am I), so you should be able to follow along with just a very basic understanding of VHDL.

Overview

In order to play back an audio file via the FPGA using the Replay Framework, we need a way to select a file located on the SD card then to stream that data to the FPGA and finally to push the data out to the DAC.

The method used in this guide is almost the same as the “loader” core. A few replay.ini file changes will configure the OSD (on screen display) provided by the ARM firmware to enable selection of any file with the PCM extension. The contents of this file will then be exposed to the FPGA on channel A-0 (see later) and transfered block by block in response to FPGA requests into a queue. Each sample in the queue will then be delivered to the DAC via the Framework.

We’ll start by setting up a copy of the getting_started core followed by a brief orientation on the core/framework hierarchy and then dive into the changes needed to configure clocks, the file IO protocol and the core implementation itself.

You can download the final project source produced by following this guide for reference should any part of the guide’s instructions confuse.

Credits

I want to thank MikeJ for helping clear up my misunderstanding of several parts of the Generic IO Protocol and Framework in general as well as members of the FPGA Replay forum, their many posts helped speed my learning. I hope this guide helps in turn to speed yours.